Get Serdes Verilog Code

A serializer/deserializer (serdes or SerDes)* circuit converts parallel data—in other words, multiple streams of data—into a serial (one bit) stream of data that is transmitted over a high-speed connection, such as LVDS, to a receiver that converts the serial stream back to the original, parallel data.

SerDes is a functional block that Serializes and Deserializes digital data used in high-speed chip-to-chip communication.

A SerDes or serializer/deserializer is an integrated circuit (IC or chip) transceiver that converts parallel data to serial data and vice-versa. The transmitter section is a serial-to-parallel converter, and the receiver section is a parallel-to-serial converter.

SerDes is a functional block that Serializes and Deserializes digital data used in high-speed chip-to-chip communication.

The phase-locked loop (PLL) The phase-locked loop is an important part of any SerDes device, as it produces the high-speed clock used to drive the serial transmitter as well as receive path of the device.

The basic SerDes function is made up of two functional blocks: the Parallel In Serial Out (PISO) block (aka Parallel-to-Serial converter) and the Serial In Parallel Out (SIPO) block (aka Serial-to-Parallel converter).

There are at least four distinct SerDes architectures. They include: parallel clock SerDes, 8b/10 SerDes, embedded clock bits (alias start-stop bit) SerDes, and bit interleaving SerDes.

Most SerDes devices are capable of full-duplex operation, meaning that data conversion can take place in both directions simultaneously.